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HSPICE* Signal Integrity Model and User Guide for DDR3/DDR3L
HSPICE Signal Integrity Model and User Guide for DDR3/DDR3L

Product Code: STLGRN86

Signal integrity simulation models and support documentation for the Processor DDR3 interface for the platform. This documentation describes the DDR3 Memory Interface Synopsys HSPICE* model files for the Processor on the Platform including the Model User’s Guide. A listing of the files is provided, including the file names and details of each of the file contents. Also included in this document are example system deck descriptions, guidance on running the simulations and recommendations for analyzing the results.

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