YOU MAY EXPERIENCE DELAYS IN SHIPPING AT ANY TIME DUE TO THE WORLDWIDE SEMICONDUCTOR SHORTAGE.
Please turn off compatibility mode to ensure this site displays properly. For instructions to complete this action, please click
Technical Product Support
Design-In Tools Store
Tools & Services
Server Tools, Management, and Software
Intel Romley Platform Tools
ASSET* InterTech ScanWorks* for PCIe G3 Margining
Silicon feature used to test and debug CPU Rx PCIe* Gen3 interfaces. Provides electrical test patterns for board level validation and debug. Sends multiple patterns at speed, varying receive buffer margins to generate a pseudo eye pattern that can be used for Systems Per Million (Eye Mask) calculations to gauge performance. Provides electrical test patterns and analysis for board level validation and debug and HVM testing. Can be done in-band. Software and hardware are available from the third party tool vendor listed.
Log in for more information.
(Your shopping cart is empty)