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ASSET* InterTech ScanWorks* for PCIe G3 Margining
ASSET InterTech ScanWorks for PCIe G3 Margining

Product Code: STLGRN69

Silicon feature used to test and debug CPU Rx PCIe* Gen3 interfaces. Provides electrical test patterns for board level validation and debug. Sends multiple patterns at speed, varying receive buffer margins to generate a pseudo eye pattern that can be used for Systems Per Million (Eye Mask) calculations to gauge performance. Provides electrical test patterns and analysis for board level validation and debug and HVM testing. Can be done in-band. Software and hardware are available from the third party tool vendor listed.

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